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A new parallel hardware architecture for high-performance stereo matching calculation

  • Published:2015-09 Issue: Volume:51 Page:81-91
  • ISSN:0167-9260
  • Container-title:Integration, the VLSI Journal
  • language:en
  • Short-container-title:Integration, the VLSI Journal

Author:

Seo Young-Ho,Yoo Ji-Sang,Kim Dong-Wook

Funder

Ministry of Science, ICT and Future Planning

National Research Foundation of Korea

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference19 articles.

1. A taxonomy and evaluation of dense two-frame stereo correspondence algorithms;Scharstein;Int. J. Comput. Vis.,2002

2. Advances in computational stereo;Brown;IEEE Trans. Pattern Anal. Mach. Intell.,2003

3. Video Processing and Communications;Wang,2002

4. J. Woodfill, B. von Herzen, R. Zabih, Frame-rate robust stereo on a PCI board (1998). 〈http://www.cs.cornell.edu/rdz/Papers/Archive/fpga.pdf〉.

5. Stereo matching using belief propagation;Sun;IEEE Trans. Pattern Anal. Mach. Intell.,2003

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