1. CMOS VCO׳s for PLL frequency synthesis in GHz digital mobile radio communications;Thamsirianunt;IEEE J. Solid-State Circuits,1997
2. L. Wu, H. Chen, S. Nagavarapu, R. Geiger, E. Lee, and W. Black, A monolithic 1.25Gbits/sec CMOS Clock/Data Recovery Circuit for Fiber Channel Transceiver, in: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol.2, pp. 565–568, 1999.
3. A CMOS clock recovery circuit for 2.5-Gb/s NRZ data;Anand;IEEE J. Solid-State Circuits,2001
4. A fully integrated 24-GHz eight-element phased-array receiver in silicon;Guan;IEEE J. Solid-State Circuits,2004
5. A 77-GHz phased-array transceiver with on-chip antennas in silicon: receiver and antennas;Babakhani;IEEE J. Solid-State Circuits,2006