An energy-efficient fault-aware core mapping in mesh-based network on chip systems

Author:

Beechu Naresh Kumar Reddy,Moodabettu Harishchandra Vasantha,Yernad Balachandra Nithin Kumar

Funder

Department of Electronics and Information Technology, Ministry of Communication & IT, Government of India

Media Lab Asia

Publisher

Elsevier BV

Subject

Computer Networks and Communications,Computer Science Applications,Hardware and Architecture

Reference24 articles.

1. An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architectures;Agrawal,2010

2. System level fault-tolerance core mapping and FPGA-based verification of NoC;Beechu;Microelectron. J.,2017

3. High-performance and energy-efficient fault-tolerance core mapping in NoC;Beechu;Sustain. Comput. Inform. Syst.,2017

4. Cycle-accurate network on chip simulation with Noxim;Catania;ACM Trans. Model Comput. Simulat.,2016

5. FARM: fault-Aware resource management in NoC based multiprocessor platforms;Chou,2011

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