Assessing merged DRAM/Logic technology-Reference-Cited by-同舟云学术

Assessing merged DRAM/Logic technology

Published:1999-07 Issue:2 Volume:27 Page:179-194
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Kim Ytong-Bin,Chen Tom W.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference12 articles.

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2. P.M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Combined DRAM and logic chip for massively parallel systems, Proceedings of 16th Conference on Advanced Research in VLSI, March 1995, pp. 4–16.

3. Akira Kanuma, The best DRAM approach for graphics application, ISSCC95/Evening Discussion Session/WE2, February 1995, pp. 96–97.

4. Toshio Sunaga, The best DRAM approach for graphics application, ISSCC95/Evening discussion Session/WE2, February 1995, pp. 96–97.

5. M.D. Weir, J.F. Kita, T.J. Cockerill, P.F. Hynek, T.M. Lepsic, T.K. Ta, B.K. Wong, S.R. Woodham, R.R. Young, A 250K-circuit ASIC family using a DRAM technology, Proceedings of IEEE 1990 CICC, 1990, pp. 4.6.1–4.6.5.

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