Performance optimization of VLSI interconnect layout-Reference-Cited by-同舟云学术

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Performance optimization of VLSI interconnect layout

Published:1996-11 Issue:1-2 Volume:21 Page:1-94
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Cong Jason,He Lei,Koh Cheng-Kok,Madden Patrick H.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference202 articles.

1. National Technology Roadmap for Semiconductors;Semiconductor Industry Association,1994

2. Circuits, Interconnections, and Packaging for VLSI;Bakoglu,1990

3. Coping with RC(L) interconnect design headaches;Pileggi,1995

4. Signal delay in RC tree networks;Rubinstein;IEEE Trans. Comput.-Aided Des.,1983

5. The transient response of damped linear networks with particular regard to wide-band amplifiers;Elmore;J. Appl. Phys.,1948

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