Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures-Reference-Cited by-同舟云学术

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Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures

Published:2024-09 Issue: Volume:9 Page:100716
ISSN:2772-6711
Container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy
language:en
Short-container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy

Author:

Lit Asrani^ORCID,Husin Maimun Huja,Suhaili Shamsiah^ORCID

Publisher

Elsevier BV

Reference51 articles.

1. On-chip interconnection architecture of the tile processor;Wentzlaff;IEEE Micro,2007

2. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives;Marculescu;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2009

3. Knights landing: second-generation Intel Xeon Phi product;Sodani;IEEE Micro,2016

4. Scorpio: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering;Daya;ACM SIGARCH Comput. Archit. News,2014

5. The raw microprocessor: a computational fabric for software circuits and general-purpose programs;Taylor;IEEE Micro,2002

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