Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Author:

Fadl Omnia S.,Abu-Elyazeed Mohamed F.,Abdelhalim Mohamed B.,Amer Hassanein H.,Madian Ahmed H.

Publisher

Elsevier BV

Subject

Multidisciplinary

Reference18 articles.

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits;Microelectronics Journal;2024-04

2. Regression Analysis Based Circuit Power Estimation Technique;2023 International Conference on Evolutionary Algorithms and Soft Computing Techniques (EASCT);2023-10-20

3. The Meritorious Effects of Machine Learning Algorithms in Assessment of Power Consumption by Arithmetic Circuits in IC Design;2023 Fifth International Conference on Electrical, Computer and Communication Technologies (ICECCT);2023-02-22

4. SoK;Proceedings of the 2022 ACM on Asia Conference on Computer and Communications Security;2022-05-30

5. Aspects of Low-Power High-Speed CMOS VLSI Design: A Review;Lecture Notes in Networks and Systems;2017-07-21

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