Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

Author:

Jegadheesan V.ORCID,Sivasankaran K.,Konar Aniruddha

Publisher

Elsevier BV

Subject

Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science

Reference37 articles.

1. Dimensioning for power and performance under10 nm: the limits of FinFETs scaling;Bardon;Proc. ICICDT,2015

2. Challenges of 10 nm and 7 nm CMOS for server and mobile applications;Divakaruni;ECS Trans.,2016

3. N. Loubet, et al., Stacked nanosheet gate-all_around transistor to enable scaling beyond FinFET, in: Proceedings of IEEE Symposium on VLSI Technology Digest of Technical Papers, 2017.

4. Device exploration of nanosheet transistors for sub-7-nm technology node;Jang;IEEE Trans. Electron Devices,2017

5. Vertically integrated multiple nanowire field effect transistor;Lee;Nano Lett.,2015

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