Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap-Reference-Cited by-同舟云学术

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Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap

Published:2019-11 Issue: Volume:103 Page:104605
ISSN:1369-8001
Container-title:Materials Science in Semiconductor Processing
language:en
Short-container-title:Materials Science in Semiconductor Processing

Author:

Joseph H. Bijo,Singh Sankalp Kumar,Hariharan R.M.,Tarauni Yusuf,Thiruvadigal D. John

Funder

Centre for Material Science and Nano devices

Dept of Physics & Nanotechnology

Faculty of Engineering and Technology, SRMIST, Chennai, India

Publisher

Elsevier BV

Subject

Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science

Reference30 articles.

1. Prospect of tunneling green transistor for 0.1V CMOS;Hu,2010

2. Performance comparison between p-i-n tunneling transistors and conventional MOSFETs;Koswatta;IEEE Trans. Electron Devices,2009

3. Double-gate tunnel FET with High-$\kappa$ gate dielectric;Boucart;IEEE Trans. Electron Devices,2007

4. Down to the wire;Corcoran;Sci. Am.,1990

5. Tunnel field-effect transistors as energy-efficient electronic switches;Ionescu;Nature,2011

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analyze the Effect of Hetero Material and Dielectric on TFET with Dual Work Function Engineering;Nanoscience & Nanotechnology-Asia;2024-02

2. Temperature Influence on Dielectric Tunnel FET Characterization and Subthreshold Characterization;Silicon;2022-04-13

3. Assessment of ITCs on Dual Metal Strip Based Charge plasma TFET: Analog to Linearity analysis;2022 IEEE Delhi Section Conference (DELCON);2022-02-11

4. Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application;Silicon;2022-01-25

5. A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications;Microelectronics Journal;2021-08

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