Chained backplane communication architecture for scalable multiprocessor systems

Author:

Kolinummi Pasi,Hämäläinen Timo,Saarinen Jukka

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference36 articles.

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2. B.P. Aichinger, Futurebus+as an I/O Bus: Profile B, in: 19th Annual Int’l Symposium on Computer Architecture, Computer Architecture News, May 1992, ACM Press, New York, 20 (2) 300–307

3. ANSI/IEEE standards 896.1x and 896.2x, Standard for Futurebus+®, IEEE Service Center, Piscataway, New York, 1991

4. ANSI/IEEE standard 1296, Multibus II standard, IEEE Service Center, Piscataway, New York, 1987

5. ANSI/IEEE standard 1596, Scalable Coherent Interface Standard, IEEE Service Center, Piscataway, New York, 1992

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