Author:
Lopacinski Lukasz,Brzozowski Marcin,Kraemer Rolf,Büchner Steffen,Nolte Jörg
Subject
Electrical and Electronic Engineering
Reference36 articles.
1. Lopacinski L, Buechner S, Kraemer R. Parallel RS error correction structures dedicated for 100Gbps wireless data link layer. In: Ubiquitous Wireless Broadband (ICUWB), 2015 IEEE International Conference on; 2015.
2. “VC709 Evaluation Board for the Virtex-7 FPGA - User Guide”. Xilinx Datasheet; 2014.
3. Lopacinski L, Brzozowski M, Kraemer R. A 100Gbps data link layer with an adaptive algorithm for forward error correction. In: Proceedings of 2015 IEICE ICTF; 2015.
4. 60GHz broadband MAC system design for cable replacement in machine vision applications;Ehrig;AEU – Int J Electron Commun,2013
5. Data link layer considerations for future 100Gbps terahertz band transceivers;Lopacinski;J Wireless Commun Mobile Comput,2017
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4 articles.
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