A new flip-flop based on discrete-time parametric amplifier-Reference-Cited by-同舟云学术

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A new flip-flop based on discrete-time parametric amplifier

Published:2020-03 Issue: Volume:116 Page:153054
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Ghavidel Jaliseh Mehdi,Nabavi Abdolreza,Saeidpour Azar Hadi,Amini-sheshdeh Jila

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference29 articles.

1. Nanosecond NMOS VLSI Current Mode Logic;Elmasry;IEEE J Solid-State Circuits,1982

2. Power–delay–area–noise margin tradeoffs in positive-feedback MOS current-mode logic;Alioto;IEEE Trans Circuits Syst I Regul Pap,2007

3. Razavi B. Charge steering: A low-power design paradigm. In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference 2013. http://doi.org/10.1109/cicc.2013.6658443.

4. Hassan KM, Ibrahim SA. A Non-Return-to-Zero Charge-Steering Flip-Flop for High-Speed Wireline Transceivers. 2019 IEEE Jordan International Joint Conference on Electrical Engineering and Information Technology (JEEIT). 2019. http://doi.org/10.1109/jeeit.2019.8717486.

5. Dynamic current mode logic (DyCML): a new low-power high-performance logic style;Allam;IEEE J Solid-State Circuits,2001

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A new boosted charge-steering latch for high-speed low-power applications;AEU - International Journal of Electronics and Communications;2020-09

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