A 2.4 mW, +11.3 dBm IIP3 and 17 dB conversion gain CMOS mixer with capacitor cross-coupled and modified post distortion techniques

Author:

Yi Lai Chi,Ramiah Harikrishnan,Vitee Nandini,Rajendran Jagadheswaran

Funder

Motorola Foundation

UM Partnership

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference18 articles.

1. DC-coupled IF stage design for a 900-MHz ISM receiver;Harjani;IEEE J Solid-State Circuits,2003

2. A low power high-performance area efficient RF front-end exploiting body effect for 2.4 GHz IEEE 802.15. 4 applications;Gladson;AEU-Int J Electron Commun,2018

3. High linearity, low power RF mixer design in 65 nm CMOS technology;Mahmou;AEU-Int J Electron,2014

4. A new RF CMOS Gilbert mixer with improved noise figure and linearity;Yoon;IEEE Trans Microw Theory Tech,2008

5. A low-voltage folded-switching mixer in 0.18-µm CMOS;Vidojkovic;IEEE J Solid-State Circuits,2005

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1. A 45MHz-2.5GHz broadband CMOS up-conversion mixer with a bisymmetric class-AB input stage;IEICE Electronics Express;2022-11-25

2. Recent advancement in the design of mixers for software‐defined radios;International Journal of RF and Microwave Computer-Aided Engineering;2021-11-08

3. A 1.5–7 GHz wideband low-voltage low-power switched transconductor up-conversion mixer;AEU - International Journal of Electronics and Communications;2021-05

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