Performance/price estimates for cortex-scale hardware: A design space exploration-Reference-Cited by-同舟云学术

Performance/price estimates for cortex-scale hardware: A design space exploration

Published:2011-04 Issue:3 Volume:24 Page:291-304
ISSN:0893-6080
Container-title:Neural Networks
language:en
Short-container-title:Neural Networks

Author:

Zaveri Mazad S.,Hammerstrom Dan

Publisher

Elsevier BV

Subject

Artificial Intelligence,Cognitive Neuroscience

Reference55 articles.

1. Reverse engineering the brain;Albus,2008

2. Scaling constraints in nanoelectronic random-access memories;Amsinck;Nanotechnology,2005

3. Ananthanarayanan, R., & Modha, D. S. (2007). Anatomy of a cortical simulator. Paper presented at the ACM/IEEE conf. on high performance networking and computing: supercomputing.

4. Bailey, J. L. (1993). A VLSI interconnect strategy for biologically inspired artificial neural networks. Ph.D. dissertation. Oregon grad. inst. of sci. & tech. Beaverton, OR.

5. Bailey, J., & Hammerstrom, D. (1988). Why VLSI implementations of associative VLCNs require connectionmultiplexing. Paper presented at the Proc. IEEE intl. conf. on neural networks.

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