1. State-of-the-Art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS”;Staszweski;IEEE Trans. Circ. Syst. I: Regul. Pap.,2011
2. A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65nm CMOS;Rylyakov,2008
3. A design procedure for all-digital phase-locked loop based on a charge-pump phase-locked loop analogy;Kratyuk;IEEE Trans. Circ. Syst. II,2007
4. An ultra-low power 1.7-2.7 GHz fractional-N sub-sampling digital frequency synthesizer and modulator for IoT applications in 40 nm CMOS”;Liu;IEEE Trans. Circ. Syst. I: Regul. Pap.,2017
5. A mixed mode design flow for Multi GHz ADPLLs;Shakir,2011