Process corner detection by skew inverters for 500MHZ 2×VDD output buffer using 40-nm CMOS technology-Reference-Cited by-同舟云学术

Process corner detection by skew inverters for 500MHZ 2×VDD output buffer using 40-nm CMOS technology

Published:2015-01 Issue:1 Volume:46 Page:1-11
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Wang Chua-Chin,Lu Wen-Je,Juan Kai-Wei,Lin Wei,Tseng Hsin-Yuan,Juan Chun-Ying

Funder

Metal Industries Research Development Centre (MIRDC) and Ministry of Economic Affairs

National Science Council

Southern Taiwan Science Park Administration (STSPA)

Publisher

Elsevier BV

Subject

General Engineering

Reference25 articles.

1. Wide-range 5.0/3.3/1.8V I/O buffer using 0.35-μm 3.3-V CMOS technology;Lee;IEEE Trans. Circuits Syst.-I, Reg. Pap.,2009

2. A 1/2 VDD to 3 × VDD bidirectional I/O buffer with a dynamic gate bias generator;Wang;IEEE Trans. Circuits Syst .-I, Reg. Pap.,2010

3. 0.9V to 5V bidirectional mixed-voltage I/O buffer with an ESD protection output stage;Wang;IEEE Trans. Circuits Syst.-II, Exp. Briefs,2010

4. M.-D. Ker, T.-M. Wang, F.-L. Hu, Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process, in: Proceedings of IEEE International Conference on Electronics, Circuits and Systems, Sep. 2008, pp. 1047–1050.

5. New design of 2×VDD-Tolerant power-rail ESD clamp circuit for mixed-voltage I/O buffers in 65-nm CMOS technology;Yeh;IEEE Trans. Circuits Syst.-II, Exp. Briefs,2003

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