A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors-Reference-Cited by-同舟云学术

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A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors

Published:2023-01 Issue: Volume:131 Page:105630
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Liu Mengyu,Zhu Sihui,Xu Yue

Funder

National Natural Science Foundation of China

Jiangsu Provincial Key Research and Development Program

Jiangsu Agricultural Science and Technology Innovation Fund

Publisher

Elsevier BV

Subject

General Engineering

Reference23 articles.

1. CMOS image sensors: electronic camera-on-a-chip;Fossum;IEEE Trans. Electron. Dev.,1997

2. A 368× 184 optical under-display fingerprint sensor comprising hybrid arrays of global and rolling shutter pixels with shared pixel-level ADCs;Yin;IEEE J. Solid State Circ.,2021

3. A 51-pJ/pixel 33.7-dB PSNR 4× compressive CMOS image sensor with column-parallel single-shot compressive sensing;Park;IEEE J. Solid State Circ.,2021

4. 2.45 e-RMS low-random-noise, 598.5 mW low-power, and 1.2 kfps high-speed 2-mp global shutter CMOS image sensor with pixel-level ADC and memory;Seo;IEEE J. Solid State Circ.,2022

5. A 12-bit column-parallel two-step single-slope ADC with a foreground calibration for CMOS image sensors;Zhang;IEEE Access,2020

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3. Comparative Analysis of Design Parameters for Modern Radio Frequency Complementary Metal Oxide Semiconductor Ultra-Low Power Amplifier Architecture Trends;IEEC 2023;2023-09-20

4. A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors;Integration;2023-07

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