1. A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers;Shanker;IEEE Trans. Device Mater. Reliab.,2014
2. A unified approach for performance degradation analysis from transistor to gate level;Hussain;Int. J. Electr. Comput. Eng.,2018
3. Performance analysis of double gate n-FinFET using high-k dielectric materials;Kumar;International Journal of Innovative Research in Science, Engineering and Technology,2016
4. Investigation of junction-less double gate MOSFET with high-k gate-oxide and metal gate layers;Ambika;Int. J. Innovative Technol. Explor. Eng.,2019
5. “Quantum Effect Dependent Modelling of Short Channel Junctionless Double Gate Stack (SC-JL-DG) MOSFET for Analog Applications” Microelectronics Journal;Udar,2023