Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET-Reference-Cited by-同舟云学术

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Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET

Published:2024-03 Issue: Volume:145 Page:106122
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Singh Devenderpal^ORCID,Chaudhary Shalini,Dewan Basudha,Yadav Menka

Publisher

Elsevier BV

Reference45 articles.

1. Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs;Suzuki;IEEE Trans. Electron Devices,2000

2. Multiple-gate soi mosfets;Colinge;Solid-State Electron.,2004

3. FinFETs: From devices to architectures;Bhattacharya;Adv. Electron.,2014

4. Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering;Bousari;AEU-Int. J. Electron. Commun.,2019

5. Super-threshold semi analytical channel potential model for DG tunnel FET;Yadav;J. Comput. Electron.,2015

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterizing parameter variations for enhanced performance and adaptability in 3 nm MBCFET technology;Microelectronics Journal;2024-09

2. Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM;Physica Scripta;2024-07-12

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