Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65nm CMOS technology
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Published:2007-06
Issue:6-7
Volume:38
Page:783-786
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ISSN:0026-2692
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Container-title:Microelectronics Journal
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language:en
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Short-container-title:Microelectronics Journal
Subject
General Engineering
Reference8 articles.
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2. J. Yugami, et al., Adanced oxynitride gate dielectrics for CMOS applications, in: IWGI, 2003, p. 140.
3. H.Y. Yu, et al., in: IEDM, 2003, p. 99.
4. C. Lombardi, et al., A physically based mobility model for numerical simulation of nonplanar devices, IEEE Trans. Comput.-Aid. Des. 7(11) 1164.
5. Electron and hole mobility in silicon at large operating temperatures part I-bulk mobility;Reggiani;IEEE Trans. Electron. Dev.,2002
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