Impact of dual-k spacer on analog performance of underlap FinFET-Reference-Cited by-同舟云学术

Impact of dual-k spacer on analog performance of underlap FinFET

Published:2012-11 Issue:11 Volume:43 Page:883-887
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Nandi Ashutosh,Saxena Ashok K.,Dasgupta S.

Publisher

Elsevier BV

Subject

General Engineering

Reference28 articles.

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4. Design and analysis of sub-DT sub-domino logic circuits for ultra low power applications;Nandi;J.Low Power Electron.,2010

5. FinFET process refinements for improved mobility and gate work function engineering;Choi;IEDM Tech. Dig.,2002

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