Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software
Reference30 articles.
1. T. Bhatt, V. Sundaramurthy, V. Stolpman, D. McCain, Pipelined block-serial decoder architecture for structured ldpc codes, in: Acoustics, Speech and Signal Processing, 2006, ICASSP 2006 Proceedings, 2006 IEEE International Conference on, vol. 4, 2006, pp. IV–IV, doi:10.1109/ICASSP.2006.1660946.
2. Legup: high-level synthesis for fpga-based processor/accelerator systems;Canis,2011
3. High-level synthesis for fpgas: from prototyping to deployment;Cong;Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on,2011
4. Massively ldpc decoding on multicore architectures;Fernandes;IEEE Transactions on Parallel and Distributed Systems,2011
5. Low-density parity-check codes;Gallager;Information Theory, IRE Transactions on,1962
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