Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores

Author:

Rathor MahendraORCID,Anshul AdityaORCID,Bharath K,Chaurasia RahulORCID,Sengupta Anirban

Funder

Indian Institute of Technology Indore

Indian Institute of Technology (BHU) Varanasi

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference25 articles.

1. Securing hardware accelerators: a new challenge for high-level synthesis;Pilato;IEEE Embed Syst Lett,2018

2. DSPs evolving in consumer electronics applications;Schneiderman;IEEE Signal Process Mag,2010

3. Guest editorial securing IoT hardware: threat models and reliable, low-power design solutions;Sengupta;IEEE Trans Very Large Scale Integr (VLSI) Syst,2017

4. IP core steganography using switch based key-driven hash-chaining and encoding for securing DSP kernels used in CE systems;Rathor;IEEE Trans Consum Electron,2020

5. Can EDA combat the rise of electronic counterfeiting?;Koushanfar,2012

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