Low power high performance priority encoder using 2D-array to 3D-array conversion-Reference-Cited by-同舟云学术

Low power high performance priority encoder using 2D-array to 3D-array conversion

Published:2020 Issue: Volume:171 Page:1037-1045
ISSN:1877-0509
Container-title:Procedia Computer Science
language:en
Short-container-title:Procedia Computer Science

Author:

Chandra K Anil,Murty N S

Publisher

Elsevier BV

Subject

General Engineering

Reference12 articles.

1. Kun C, Quan S, Mason A. A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512) 2004May 23 (Vol. 2, pp. 11–753). IEEE.

2. A VLSI high-performance priority encoder using standard CMOS library;Abdel-Hafeez;IEEE Transactions on Circuits and Systems II: Express Briefs,2006

3. Maurya SK, Clark LT. Fast and scalable priority encoding using static CMOS. InProceedings of 2010 IEEE International Symposium on Circuits and Systems 2010 May 30 (pp. 433-436). IEEE.

4. Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques;Huang;IEEE Journal of Solid-State Circuits,2002

5. Huang SW, Chang YJ. A full parallel priority encoder design used in comparator. In2010 53rd IEEE International Midwest Symposium on Circuits and Systems 2010 Aug 1 (pp. 877-880). IEEE.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23

2. A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-01-07