5 V compatibility with 3.3 V-only CMOS ASICs-Reference-Cited by-同舟云学术

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5 V compatibility with 3.3 V-only CMOS ASICs

Published:1992-12 Issue:8 Volume:23 Page:577-580
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Henderson Brian,Gal Laszlo

Publisher

Elsevier BV

Subject

General Engineering

Reference6 articles.

1. A 200 MHz 64b Dual-Issue CMOS Microprocessor;Dobberpuhl,1992

2. ICs Going on a 3-V Diet;Prince;IEEE Spectrum,1992

3. The Super ASICs of Tomorrow Will Replace a System on a Chip;Laszlo;Electronic Engineering Times,1992

4. Acceleration Factors for Thin Gate Oxide Stressing;McPherson,1985

5. Bipolar and MOS analogue Integrated Circuit Design;Grebene,1984

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Transistor controlled slew rate process independent PCI compliant I/O buffer with possible power/delay trade-off;Microelectronics Journal;1998-10

2. CMOS technology for mixed signal ICs;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;1997-08

3. CMOS technology for mixed signal ICs;Solid-State Electronics;1997-07

4. A 3/5 V compatible I/O buffer;IEEE Journal of Solid-State Circuits;1995-07

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