Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Author:

Voldman Steven H.,Gross Vaughn P.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Biotechnology,Electronic, Optical and Magnetic Materials

Reference21 articles.

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2. Determination of threshold failure levels of semiconductor diodes and transistors due to pulsed voltages;Wunsch;IEEE Trans. Nucl. Sci.,1968

3. Pulse power failure modes in semiconductor;Tasca;IEEE Trans. Nucl. Sci.,1970

4. Semiconductor junction non-linear failure power thresholds: Wunsch-Bell revisited;Ash,1983

5. Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology;Voldman,1993

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2. ESD Design Synthesis;The ESD Handbook;2021-03-26

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4. ESD Architecture and Floor Planning;The ESD Handbook;2021-03-26

5. VO2 Switch for Electrostatic Discharge Protection;IEEE Electron Device Letters;2020-02

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