1. Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors;Singh;International Journal of Electrical and Computer Engineering,2020
2. Design of Low Power Si 0.7 Ge 0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology;Tripathi;Wirel. Personal Commun.,2019
3. Performance Enhancement of Triple Material Double Gate TFET with Heterojunction and Heterodielectric;Vimala;Solid State Electron. Lett.,2019
4. Comparative Study of InGaN and InGaAs Based Dopingless TFET with Different Gate Engineering Techniques;Sharma;Adv. Nat. Sci; Nanosci. Nanotechnol.,2019
5. Varun Mishra, Yogesh K Verma, Santosh K Gupta Surface Potential BasedAnalysis of FerroelectricDualMaterialGateAllAround (FE-DMGAA)TFETs.WILEY online library,3 January 2020 p(1-11)