14-T hybrid full adder design and its implementation for high-performance arithmetic applications-Reference-Cited by-同舟云学术

14-T hybrid full adder design and its implementation for high-performance arithmetic applications

Published:2022 Issue: Volume:69 Page:454-458
ISSN:2214-7853
Container-title:Materials Today: Proceedings
language:en
Short-container-title:Materials Today: Proceedings

Author:

Mohammed Abdul Azeem,Prasanna N.V.S.S.,Harish Kumar K.V.,Banu Teja K.

Funder

Vignan's Foundation for Science, Technology and Research

Publisher

Elsevier BV

Subject

General Medicine

Reference19 articles.

1. Design of low-voltage power efficient frequency dividers in folded MOS current mode logic;Centurelli;IEEE Trans. Circuits Syst. I Regul. Pap.,2020

2. kumar, V.V. & nadha, V.V., 2014. Design and Simulation of High Speed CMOS Full Adder. International Journal of Engineering Trends and Technology, 15(4), pp.191–195. Available at: http://dx.doi.org/10.14445/22315381/ijett-v15p237

3. High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell;Kandpal;IEEE Trans. VLSI Syst.,2020

4. Modified Low-Power Hybrid 1-Bit Full Adder;Mannepalli,2018

5. “Robust & energy efficient universal gates for high performance computer networks at 22nm process technology”;Priya;Int. J. Electric. Comput. Eng.,2014

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