Author:
Malladhi Nagarjuna,Attimarad Girish V.
Reference10 articles.
1. Circuits Interconnections and Packaging for VLSI;Bakoglu,1990
2. Predictive Technology Model (PTM), http://ptm.asu.edu.
3. F. Hasani, N. Masoumi, Crosstalk and delay optimization techniques for nano scale interconnects, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Rabat, pp. 159-163, 2007.
4. K.T. Tang, E.G. Friedman, Delay and power expressions characterizing a CMOS inverter driving an RLC load, in: Proceedings of the IEEE International Symposium Circuits and Systems, pp. 4.269–4.272, 2000.
5. T. Sakurai, A.R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, in IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584–594, April 1990.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献