1. Tulasi Radhika Patnala, Jayanthi D, Shylu D.S, Kavitha K, Prathyusha Chowdary, Maximal length test pattern generation for the cryptography applications https:// www.sciencedirect.com /science /article /pii /S2214785320305368, materials today proceedings, In press, available online from 20.02.2020.
2. Tulasi Radhika Patnala, Jayanthi D, Sankararao Majji, Manohar Valleti, Srilekha Kothapalli, Santhosh Chandra Rao Karanam, Modernistic way for KEY Generation for Highly Secure Data Transfer in ASIC Design Flow https://ieeexplore.ieee.org/document/9074200, Published in IEEE digital Xplore, Electronic ISSN: 2575-7288, available from 23.04.2020.
3. Tulasi Radhika Patnala, Sankararao Majji, Gopala Krishna Pasumarthi, Optimization of CSA for Low Power and High-Speed using MTCMOS and GDI Techniques https://www.ijeat.org/wp-content /uploads /papers /v8i5S3/E10620785S319.pdf, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-8 Issue-5S3, July, 2019.
4. Sankararao Majji, Tulasi Radhika Patnala, Manohar Valleti, Srilekha Kothapalli, Santhosh Chandra Rao Karanam, “A Study on the Comprehensive Analysis of Electro Migration for the Nano technology trends”, Published in IEEE digital Xplore, Electronic ISSN: 2575-7288, available from 23.04.2020
5. Sajja Krishna Kishore; Tulasi Radhika Patnala; Arun S Tigadi; Aatif Jamshed “An On-chip Analysis of the VLSI designs under Process Variations” published in IEEE digital Xplore, 2020 International Conference on Smart Electronics and Communication (ICOSEC).