1. A network on chip architecture and design methodology;Kumar,2002
2. Networks on chips: a new SoC paradigm;Benini;IEEE Mag.,2002
3. Coding for reliable on-chip buses: a class of fundamental bounds and practical codes;Sridhara;IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.,2007
4. Testing SoC interconnects for signal integrity using boundary scan;Tehranipour,2003
5. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip;Zimmer,2003