Power optimization for application-specific networks-on-chips: A topology-based approach

Author:

Elmiligi Haytham,Morgan Ahmed A.,El-Kharashi M. Watheq,Gebali Fayez

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference36 articles.

1. Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors;Meyer;IEEE Transactions on Computers,2005

2. N. Banerjee, P. Vellanki, K.S. Chatha, A power and performance model for network-on-chip architectures, in: Proceedings of the Design, Automation and Test in Europe (DATE’04), Paris, France, 2004, pp. 21250–21256.

3. Managing power consumption in networks on chips;Simunic;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2004

4. S. Bhat, Energy models for networks-on-chip components, Master’s thesis, Technische University Eindhoven, Eindhoven, Netherlands, December 2005.

5. Saving power by synthesizing gated clocks for sequential circuits;Benini;IEEE Design and Test,1994

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