Multithreading on reconfigurable hardware: An architectural approach-Reference-Cited by-同舟云学术

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Multithreading on reconfigurable hardware: An architectural approach

Published:2012-11 Issue:8 Volume:36 Page:695-704
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Zaykov Pavel G.,Kuzmanov Georgi

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference26 articles.

1. The MOLEN μρ-coded processor;Vassiliadis,2001

2. MT-ADRES: multithreading on coarse-grained reconfigurable architecture;Wu,2007

3. UltraSONIC: a reconfigurable architecture for video image processing;Haynes,2002

4. P.G. Zaykov, G.K. Kuzmanov, G.N. Gaydadjiev, Reconfigurable multithreading architectures: a survey, in: Proc. Int’l Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS-IX), 2009, pp. 263–274.

5. Run-time support for heterogeneous multitasking on reconfigurable SoCs;Marescaux;Integr. VLSI J.,2004

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Parallelised Multithreaded Applications on a 4-core Field Programmable Gate Array (FPGA) Architecture;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2022-05

2. Hybrid swarm intelligent parallel algorithm research based on multi-core clusters;Microprocessors and Microsystems;2016-11

3. RTOS acceleration in an MPSoC with reconfigurable hardware;Computers & Electrical Engineering;2016-07

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