Dependable design technique for system-on-chip-Reference-Cited by-同舟云学术

Dependable design technique for system-on-chip

Published:2008-03 Issue:3-4 Volume:54 Page:452-464
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Kubalík Pavel,Kubátová Hana

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference46 articles.

1. R. Dobiáš, H. Kubátová, FPGA based design of raiway’s interlocking equipment, in: Proceedings of the EUROMICRO Symposium on Digital System Design, Piscataway: IEEE, 2004, pp. 467–473.

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3. Actel Corporation.: “Historic Phoenix Mars Mission Flies Actel RTAX-S Devices”, www.actel.com, 2007.

4. L. Sterpone, M. Violante, A design flow for protecting FPGA-based systems against single event upsets, DFT2005, in: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436–444.

5. QuickLogic Corporation.: Single Event Upsets in FPGAs, 2003, .

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