High performance VLSI modules for division and square root

Author:

Cappuccino Gregorio,Corsonello Pasquale,Cocorullo Giuseppe

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference12 articles.

1. Radix digit-serial pipelined divider/square-root architecture;Bashagha;IEE Proc. — Comp. Digit. Technol.,1994

2. Design and realization of a real-time processor for one bit coded SAR signals;Cappuccino;IEE Proc. — Radar Sonar Navigation,1996

3. M.D. Ercegovac, T. Lang, Division and Square Root: Digit Recurrence Algorithms and Implementations, Kluwer, Dordrecht, 1994.

4. J.A. Prabhu, G.B. Zyner, 167Mhz radix-eight divide and square root using overlapped radix-two stages, IEEE 12th Symp. on Computer Arithmetic, Los Alamitos, July 1995, IEEE Computer Society Press, pp. 155–162

5. D. Goldberg, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Matteo, CA, 1990.

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