Author:
Tunaboylu Bahadir,Soydan Ali M.
Reference11 articles.
1. Emma PG, Kursun EM. Opportunities and challenges for 3D systems and their design. IEEE Design and Test of Computers. 2009;26(5):6-14. DOI: 10.1109/MDT.2009.119
2. McCann D. Trends, challenges, and directions for silicon beyond 28 nm that drive interconnect development. In: Proceedings of IEEE Semiconductor Test Workshop, June 2015; San Diego. S01-00. pp. 1-49
3. Li J, Liao J, Ge D, Zhou C, Xiao C, Tian Q, Zhu WM. An electromechanical model and simulation for test process of the wafer probe. IEEE Transactions on Industrial Electronics. 2017;64:1284-1290. DOI: 10.1109/TIE.2016.2615273
4. Lau JH. Overview and outlook of through-silicon via (TSV) and 3D integrations. MicroElectronics International. 2011;28:8-22. DOI: 10.1108/13565361111127304
5. Zhang Y, Wang H, Sun Y, Wu K, Wang H, Cheng P, Ding GM. Copper electroplating technique for efficient manufacturing of low-cost silicon interposers. Microelectronic Engineering. 2016;150:39-42. DOI: 10.1016/j.mee.2015.11.005