A 0.014mm2 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration-Reference-Cited by-同舟云学术

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A 0.014mm2 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration

Published:2017-06 Issue: Volume: Page:
ISSN:
Container-title:2017 Symposium on VLSI Circuits
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Author:

Luo Lei,Chen Song,Zhou Minchao,Ye Tianfeng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8000695/8008441/08008507.pdf?arnumber=8008507

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-06-12

2. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. 22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024

5. A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration;IEEE Journal of Solid-State Circuits;2024

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