Exploiting transistor-level reconfiguration to optimize combinational circuits-Reference-Cited by-同舟云学术

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Exploiting transistor-level reconfiguration to optimize combinational circuits

Published:2017-03 Issue: Volume: Page:
ISSN:
Container-title:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
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Author:

Raitza Michael,Kumar Akash,Volp Marcus,Walter Dennis,Trommer Jens,Mikolajick Thomas,Weber Walter M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7919927/7926947/07927013.pdf?arnumber=7927013

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TCAD Simulations of Reconfigurable Field-Effect Transistor With Embedded-Fin-Contact to Improve On-Current;IEEE Transactions on Electron Devices;2024-05

2. Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors;Journal of Low Power Electronics and Applications;2024-04-14

3. Realization of a Complementary Full Adder Based on Reconfigurable Transistors;IEEE Electron Device Letters;2024-04

4. A Reconfigurable Ge Transistor Functionally Diversified by Negative Differential Resistance;IEEE Journal of the Electron Devices Society;2024

5. Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi‐Wire Channels;Advanced Electronic Materials;2023-12-05

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