PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation-Reference-Cited by-同舟云学术

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PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation

Published:2023-09-04 Issue: Volume: Page:
ISSN:
Container-title:2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe)
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Author:

Kohlhepp Benedikt¹,Faber Samuel¹,Kübrich Daniel¹,Dürbaum Thomas¹

Affiliation:

1. Friedrich-Alexander-Universität Erlangen-Nürnberg,Erlangen,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10264177/10264226/10264516.pdf?arnumber=10264516

Reference21 articles.

1. A New Characterization Technique for Extracting Parasitic Inductances of SiC Power MOSFETs in Discrete and Module Packages Based on Two-Port S-Parameters Measurement

2. Parasitic Inductances Extraction for SiC Power Modules Using An Enhanced Two-Port S-Parameter Approach

3. Ultra-Low Impedance Measurements Using 2-Port Measurements,2007

4. Separation measurement of parasitic impedance on a power electronics circuit board using TDR

5. Measuring of Dynamic On-State Resistance of GaN-HEMTs in Half-Bridge Application under Hard and Soft Switching Operation

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. In-Depth Study of the Parasitic Capacitances of a Half-bridge Circuit;2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe);2023-09-04

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