Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs
Author:
Affiliation:
1. Duke University,Department of Electrical and Computer Engineering,Durham,NC,USA,27708
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774511.pdf?arnumber=9774511
Reference24 articles.
1. 3D technologies for analog/RF applications
2. NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗
3. Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *
4. X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
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1. Analysis and Characterization of Defects in FeFETs;2023 IEEE International Test Conference (ITC);2023-10-07
2. Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24
3. Machine Learning in Advanced IC Design: A Methodological Survey;IEEE Design & Test;2023-02
4. Observation Point Insertion Using Deep Learning;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30
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