Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8778446/8782893/08782942.pdf?arnumber=8782942
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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3. Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications;Silicon;2022-03-12
4. Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications;Silicon;2022-03-03
5. Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications;Silicon;2022-01-10
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