Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCs
Author:
Affiliation:
1. Marvell Semiconductor, Inc.,Irvine,CA,USA
2. Synopsys, Inc.,Dublin,Ireland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137326.pdf?arnumber=10137326
Reference11 articles.
1. Within-die process variations: How accurately can they be statistically modeled?
2. Statistical Timing Analysis Under Spatial Correlations;chang;IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD),2005
3. A parametric approach for handling local variation effects in timing analysis
4. Analysis technique for systematic variation over whole shot and wafer at 45 nm process node
5. Modeling within-die spatial correlation effects for process-design co-optimization;friedberg;Proceedings International Symposium on Quality Electronic Design ISQED-02,0
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