Leakage Current Reduction in CMOS Circuits Using Stacking Technique-Reference-Cited by-同舟云学术

Leakage Current Reduction in CMOS Circuits Using Stacking Technique

Published:2020-05-20 Issue: Volume: Page:175-178
ISSN:2394-4099
Container-title:International Journal of Scientific Research in Science, Engineering and Technology
language:en
Short-container-title:IJSRSET

Author:

Rani N. Geetha¹,Ragapriya G.²,V Harshitha²,Swetha G.²,Jyothi B. Sri²

Affiliation:

1. Associate Professor, ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India

2. ECE, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India

Abstract

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

Publisher

Technoscience Academy

Subject

General Medicine

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