MoS 2 transistors with 1-nanometer gate lengths

Author:

Desai Sujay B.123,Madhvapathy Surabhi R.12,Sachid Angada B.12,Llinas Juan Pablo12,Wang Qingxiao4,Ahn Geun Ho12,Pitner Gregory5,Kim Moon J.4,Bokor Jeffrey12,Hu Chenming1,Wong H.-S. Philip5,Javey Ali123

Affiliation:

1. Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA.

2. Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA.

3. Berkeley Sensor and Actuator Center, University of California, Berkeley, CA 94720, USA.

4. Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, USA.

5. Electrical Engineering, Stanford University, Stanford, CA 94305, USA.

Abstract

A flatter route to shorter channels High-performance silicon transistors can have gate lengths as short as 5 nm before source-drain tunneling and loss of electrostatic control lead to unacceptable leakage current when the device is off. Desai et al. explored the use of MoS 2 as a channel material, given that its electronic properties as thin layers should limit such leakage. A transistor with a 1-nm physical gate was constructed with a MoS 2 bilayer channel and a single-walled carbon nanotube gate electrode. Excellent switching characteristics and an on-off state current ratio of ∼10 6 were observed. Science , this issue p. 99

Funder

U.S. Department of Energy

Applied Materials, Inc.

Entegris, Inc.

I-RiCE program

Office of Naval Research BRC

NRI SWAN Center and Chinese Academy of Sciences President's International Fellowship Initiative

Publisher

American Association for the Advancement of Science (AAAS)

Subject

Multidisciplinary

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5. M. Luisier M. Lundstrom D. A. Antoniadis J. Bokor in Electron Devices Meeting (IEDM) 2011 IEEE International (IEEE 2011) pp. 11.12.11–1.12.14.

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