Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing-Reference-Cited by-同舟云学术

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

Published:2019-05-10 Issue:6440 Volume:364 Page:570-574
ISSN:0036-8075
Container-title:Science
language:en
Short-container-title:Science

Author:

Fuller Elliot J.¹,Keene Scott T.²^ORCID,Melianas Armantas²^ORCID,Wang Zhongrui³^ORCID,Agarwal Sapan¹^ORCID,Li Yiyang¹,Tuchman Yaakov²,James Conrad D.⁴^ORCID,Marinella Matthew J.⁴,Yang J. Joshua³^ORCID,Salleo Alberto²^ORCID,Talin A. Alec¹^ORCID

Affiliation:

1. Sandia National Laboratories, Livermore, CA, USA.

2. Department of Materials Science and Engineering, Stanford University, Stanford, CA, USA.

3. Department of Computer Science and Electrical Engineering, University of Massachusetts Amherst, Amherst, MA, USA.

4. Sandia National Laboratories, Albuquerque, NM, USA.

Abstract

Ionic floating-gate memories Digital implementations of artificial neural networks perform many tasks, such as image recognition and language processing, but are too energy intensive for many applications. Analog circuits that use large crossbar arrays of synaptic memory elements represent a low-power alternative, but most devices cannot update the synaptic weights uniformly or scale to large array sizes. Fuller et al. developed an integrated device, ionic floating-gate memory, that has the gate terminal of a redox transistor electrically connected to a diffusive memristor. This low-power device enabled linear and symmetric weight updates in parallel over an entire crossbar array at megahertz rates over 10 9 write-read cycles. Science , this issue p. 570

Funder

National Science Foundation

Basic Energy Sciences

Sandia National Laboratories’ Laboratory Directed Research and Development Program

Publisher

American Association for the Advancement of Science (AAAS)

Subject

Multidisciplinary

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