200-mm wafer scale integration of high performance polycrystalline MoS2 thin film transistors

Abstract

Abstract The demand for high-performance thin-film transistors (TFTs) has increased significantly due to the increasing functionalities of electronic devices, such as displays, sensors, and computing platforms. The requirements for TFTs have also become more stringent because future electronic products necessitate denser device arrays, lower power consumption, higher mechanical flexibility, and lower-temperature processing without compromising their performance. To meet these demands, two-dimensional (2D) semiconductors are an ideal solution due to their excellent scalability, transferability, atomically thin thickness, and relatively high carrier mobility. Nevertheless, studies on 2D materials have been limited to small laboratory-scale demonstrations, focusing on proof-of-concept devices with single-crystalline 2D films. In this study, we present industrialization strategies specifically designed for polycrystalline MoS2 TFTs on a 200-mm wafer scale. We achieved nearly 100% device yield across the wafer by processing it in one of the Samsung's 200-mm fabrication facilities. We find that the metal-semiconductor junction in polycrystalline 2D MoS2 is fundamentally different from that in its single-crystalline counterpart. Thus, we redesigned the process flow to nearly eliminate the Schottky barrier height at the MoS2-metal contact, yielding excellent FET performance equivalent to that of state-of-the-art FETs fabricated from single-crystalline flakes.