Affiliation:
1. Xi’an University of Posts and Telecommunications
Abstract
Abstract
This paper presents a continuous-time linear equalizer (CTLE) with an active inductor load simultaneously connected in parallel to low frequency branch. The equalizer uses two-stage CTLE, the first stage compensating for high-frequency (HF) attenuation and the second stage equalizer compensates medium-frequency (MF) and HF by parallel low-frequency branches. The MF stage is used for the long-tail Intern symbol interference (ISI) equalization to minimize residual ISI. Equalizer with voltage control capacitor to configure the distribution of zero poles, for the HF has a configurable range of 0.5dB.The low-frequency gain can be configured by changing the load current of the active inductor to reduce the effect of parasitic resistance on the layout. The layout size is 5.9um*6um based on a 28nm CMOS process. The post layout results show that the equalizer has a maximum compensation capability of 10.37dB at a rate of 20Gb/s with an eye width of 0.85UI.
Publisher
Research Square Platform LLC
Reference20 articles.
1. Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers[J];Gondi S;IEEE Journal of solid-state circuits,2007
2. Techniques for high-speed implementation of nonlinear cancellation[J];Kasturia S;IEEE Journal on Selected Areas in Communications,1991
3. A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference[J];Lee J;IEEE Journal of Solid-State Circuits,2020
4. Wang, C., Zhu, G., Zhang, Z., et al. (2019). A 52-Gb/s sub-1pJ/bit PAM4 receiver in 40-nm CMOS for low-power interconnects[C]//2019 Symposium on VLSI Circuits. IEEE, : C274-C275.
5. A 5-Gb/s Adaptive Continuous Time Linear Equalizer Using Ferroelectric Capacitor[J];Borah D;IEEE Transactions on Components Packaging and Manufacturing Technology,2022