Affiliation:
1. IHP, Im Technologiepark, Frankfurt (Oder), Germany
Abstract
The paper presents fault-tolerant CMOS ASICs which are immune to the single
event upsets (SEU), the single event transients (SET), and the single event
latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and
SEL protection switches (SPS) make the base for a modified fault-tolerant
ASIC design flow. The proposed design flow requires the standard design
automation tools and a few additional steps during logic synthesis and layout
generation. An extra step is necessary to generate the redundant design
net-list including voters. Other two extra steps (definition of the redundant
power domains and placement of the SPS) have to be performed in the layout
phase. The concept has been proven by design and implementation of the two
digital circuits: shift-register and synchronous counter.
Publisher
National Library of Serbia
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献