Observation of lattice spacing fluctuation and strain undulation around through-Si vias in wafer-on-wafer structures using X-ray microbeam diffraction
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/53/i=5S2/a=05GE03/pdf
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1. Design of ion-implanted MOSFET's with very small physical dimensions
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3. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell
4. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
5. High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
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