Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET
Author:
Funder
Japan Science and Technology Agency
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/57/i=4S/a=04FR12/pdf
Reference34 articles.
1. Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages
2. The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family
3. A 3.6-to-1.8-V Cascode Buck Converter With a Stacked $LC$ Filter in 65-nm CMOS
4. Design of High Efficiency Integrated Voltage Regulators with Embedded Magnetic Core Inductors
5. FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs
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